Field
The present disclosure relates generally to wireless communication systems. More specifically the present disclosure related to methods and apparatus for fuse box-based memory repair.
Background
Wireless communication devices have become smaller and more powerful as well as more capable. Increasingly users rely on wireless communication devices for mobile phone use as well as email and Internet access. At the same time, devices have become smaller in size. Devices such as cellular telephones, personal digital assistants (PDAs), laptop computers, and other similar devices provide reliable service with expanded coverage areas. Such devices may be referred to as mobile stations, stations, access terminals, user terminals, subscriber units, user equipment, and similar terms.
These wireless communication devices typically use a system-on-chip (SoC) to provide many of the functions of the device. A SoC is an integrated circuit that combines all components of a computer or other electronic system on a single chip. The SoC device may contain digital, analog, mixed-signal, and radio frequency (RF) functions on a single substrate. SoCs are used widely due to their low power consumption.
A SoC may consist of a microcontroller or digital signal processor (DSP) core, memory blocks including a selection of ROM, RAM, EEPROM, and flash memory, as well as timing sources. The timing sources may include oscillators and phase-locked loops (PLL). Peripherals, including counter-timers, real-time timers, and power-on reset generators may also be incorporated. A wide variety of external and internal interfaces including analog-to-digital (ADC), digital-to-analog converters (DAC), voltage regulators and power management circuits are also typically included in a SoC. The desired performance of the end device may result in different mixes of the above functions to be included in the SoC. The SoC also includes a bus system for connecting the various functional blocks.
Testing all of the SoC components is needed to ensure that all electronic devices incorporated into user devices function correctly. This testing may be time-consuming and expensive. Most SoCs have multiple memories which may be organized into hierarchies of caches. Memories in SoCs may be tested using built-in self-test (BIST) controllers. For processors in the sub-20 nm range, the majority of failures discovered during BIST testing are single bit failures. These single bit failures may be repairable. Repairs may be accomplished using redundant rows and columns built into the memory. These redundant elements are enabled by blowing a fuse, which repairs the memory. This repair process may be improved by using a multi-way fuse decoder box for fuse box based memory repair. A multi-way or m-way fuse decoder box facilitates repair of multiple memories with a limited number of fuses.
There is a need in the art for a method and apparatus to allow repair of memory defects using a m-way fuse box-based approach.